The invention relates to a circuit stage for performing operations on the basis of arithmetical and/or logic input data A and B while taking into account any carry from a preceding stage, and for supplying an operation result as well as a carry, if any, to be applied to the next stage, which circuit stage includes a programmable data preprocessing device which is formed by a network of MOS transistors which supply the logic combination P=.alpha..multidot.A.multidot.B+.beta..multidot.A.multidot.B+.gamma..multi dot.A.multidot.B+.delta..multidot.A.multidot.B, on a "logic connection", where .alpha., .beta., .gamma., .delta. are programming parameters, a carry-propagation device which is formed by a MOS transistor inserted in a chain for propagating the carry from one stage to the next stage, the output of said chain being, moreover, precharged during a clock period in each stage, an exclusive carry propagation-generation device which comprises a transistor for discharging the chain, and a device for generating the logic result of the circuit.
A circuit of this kind is used in arithmetic and logic units of calculators, notably in microprocessors.
Circuits of this kind are described in a paper "A comparison of ALU structures for VLSI technology" by Ong and Atkins, presented at the "6th Symposium on Computer Arithmetics", held from June 20 to 22, 1983, in Aarhus (DK), and published by I.E.E.E. Computer Society; this paper discloses a device which comprises a programmable logic block for preprocessing data in order to calculate the carry, including a carry-propagation chain, and another logic block for calculating a result.